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Box 6222, Holliston, MA Legal Disclaimer: 'As always, anything said here is only opinion.' The READ ME File ---------------- 'No!

There is no try.' - Yoda It's interesting how you get to rediscover your world when you have to explain it to someone else. During and after this year's DAC, I had some Wall Street analysts ask me why I obsessed over seeing nitty-gritty customer tape-out stories for the new physical synthesis tools. My reply: 'I don't need tape-outs just for physical synthesis. I don't take *any* EDA tool seriously until I've seen that someone else has sucessfully used it to make a real, gone-into-production chip. Those new C/C++ EDA tools have the same Missing Tape-Out Problem, too.

I don't trust them either. Megaman X8 Save File Pc. ' Because although chip design is a lot like software design in many ways; there's one very important distinction between the two worlds.

Chip design is a brutally *unforgiving* world. Microsoft software engineers can cut a release of their O/S, give it to 100's of millions of people worlwide, and if there are too many bugs, they just cut another release. For the lessor bugs, you go to the Microsoft website to download specific patches. This mode of operating is pretty much true for almost all software projects be it widely used operating systems or esoteric EDA tools. But when a hardware engineer makes even a seemingly minor mistake on a chip, his company has to pay a hefty NRE to respin the chip, or worst. The Pentium Bug? It cost Intel half a billion dollars when all was said and done to clean it up.

And it was just an error that messed up some very insignificant digits in certain multiplication operations. District court in Texas ordered Toshiba to pay out $2.1 billion dollars to make ammends for an extremely subtle hardware bug with their floppy disk controller chip in their laptops. And these are just the hardware errors that make the civilian news.

In the hardcore chip design world, there are hundreds (if not thousands) of companies that, over the years, have died or were seriously stunted because of some hardware *design* problem. I'm talking completely missed market windows, or the times when competitors got there first, or the thousands of chip that just never made it to fab. It's in this brutal, unforgiving world that EDA companies peddle their wares and we chip designers have to bet our farm that their tools will mostly work as promised.

If they mess up, WE'RE the ones who will pay the piper. Take, for example, the Cadence Vampire story.

Back in the early 90's, Cadence made a killing selling a backend guy's linter tool called 'Dracula'. Technically, Dracula was a Design Rule Checker (DRC) that told you how you inadvertantly screwed up your physical design after you did that last ECO tweak of the polygons. Cadence made a lot of money off of it. The only problem was that Dracula could only run on flat designs -- it couldn't do hierarchical DRCs -- and it ran out of steam beyond a certain point.

There rival, ISS, took advantage of this weakness and created 'VeriCheck', their own hierarchical DRC tool. In the June 20, 1994 issue of EE Times, Gary Smith, then an unknown analyst from Dataquest said 'ISS is significantly taking business from Cadence. Cadence is vulnerable. After a certain number of gates, Dracula doesn't work.' So, in that Cadence fashion, Cadence started quietly telling their biggest customers that they were working on a hierarchical DRC tool called 'Vampire'.